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@Paul / @baragonaru - Here is the channel you requested.

thanks Tim!

@Tholin @namibj hi hi!

Hello i am 'kevin'

baragonaru

Hello i am 'kevin'

Sooo.... yeah, for DC behavior of SCL cells and selected primitives the "muxed e-test" should fairly straight-forward be applicable, and the "version" without reaching for extended voltage range should also be fairly compact and straight-forward. Capacitance is unfortunately not a direct derivative from it, and not something that can be measured with good accuracy and effectiveness without setting up/arranging for up-front SPICE predictions of the actual AC impedance expectations at the frequencies and DC bias conditions (incl. the PVT parts) where the AC impedance/"capacitance under not-neglecting resistive parasitics" should be measured. Ring oscillators, potentially with various combinatorial logic (that can be flexibly configured to allow excercising many more transition paths than a combinatorially entirely trivial setup could) in the oscillation's feedback/ring loop, appear the most promising substitute to actual "direct" AC capacitance measurements of DUTs under e-test conditions subject to the same boundary requirements as the "muxed e-test" of DC-behavior type. Where dynamic power needs to be measured, isolate PDNs sufficciently and employ muxed e-test measuring with 4-wire kelvin configuration for this; otherwise, set up ring oscillators that can be configured with statically decoded control lines (serially shifting in select/control bits is quite annoying to arrange for in an e-test setup, compared to performing DC multimeter measurements and select instances of frequency counting), such that only the small ring around a DUT is oscillating (into a divider reducing it as far as necessary to allow easy measurement with an off-chip frequency counter). Control lines can of course "recycle" a DUT in a ring for multiple transition paths of interest by adjusting other/non-ring inputs of the involved cells. Think a simple NAND or NOR gate in the loop blocking edge propagation when not selected, based on whether the path in question needs an extra inversion or not; there are probably a bunch of practically interesting "critical path" combinatorial arrangements that can be measured/excercised in practice here. Splitting/isolating supply voltages between paths of a single ring to allow individual dynamic power measurement and keeping the ring to as few transistors as practical should allow affordable SPICE-fitting of local mismatch modeling's random variable's individual values to squeeze out decently targeted calibration of capacitance/AC-only model parameters by taking the previously run "muxed e-test" data of dc behavior and statistical distribution of the local mismatch effects for those involved SCL cells (and of course the transistors making up those SCL cells!) as a Bayesian prior, to spend the much worse data situation of the ring oscillator setups focused on improving calibration of the capacitance/AC-only SPICE model parameters rather than wasting that measured data on parametrizing the statistical distributions of the SPICE model instance parameters (those are basically global model parameters tweaked by binning consideration effects, as applicable local surrounding geometry/mechanical-strain effects, and critically local random mismatch effects from e.g. statistically random countably-small-number-of doping atoms in the electrically sensitive region of a tiny SCL transistor) that describe the DC behavior. Even without such effort of calibrating primitive-device's SPICE models to ring oscillator measurements, it should be effective for calibrating cell-granularity (as suited for Liberty timing spec synthesis) propagation delay well enough for reliable static timing analysis.

Hey @Tholin how's the chip! @namibj things going well? @RebelMike excited to see if your run 2 chip could be used in the freework motherboard! @asic destroyer thanks for introducing us to machdyne! @Nikola @J-Lo Excited to see your USB 2.0 implementation on an async logic device! @Andrew Wingate @psychogenic @Tim 'mithro' Ansell thanks for supporting us! @baragonaru Excited for you to meet everyone working with DeepAI's slots!

We are still working on it, update towards the end of the week.

It sounds like CoBs are starting to make their way out to people, so hopefully not too long to wait on testing TQVD.

@Tholin is anyone making a "characterization" chip for probing with leads Has anyone asked John mcmaster what the requirements for a chip to be probe-able this way are? it would be great to get the physical silicon questions answered this way, if possible, and ensure it's all really probe-able

the google e-test setup would in principle still be appropriate, AFAIK, at least as far as the die layout for probing goes.